1. Field of the Invention
The present invention relates to the field of thin Film Transistor Liquid Crystal Display (TFT-LCD), and in particular to an apparatus and method for detecting the abnormal soldering of an electrostatic discharge protection chip applied in the TFT-LCD.
2. The Related Arts
TDT-LCD has already become a very important display platform of modern information technologies and video products. FIG. 1 shows a typical architecture of TFT-LCD. The main driving principle of TFT-LCD is that the control system board connects the R/G/B (red/green/blue) compressed signal, the control signal, and the power to the connector 11 which is located on the printed circuit board (PCB) through wires, leading to the LCD panel (display region 12) obtains the required powers and signals.
The signal which is sent to the PCB through the connector 11 is mainly the format of low voltage differential signaling (LVDS). Wherein, each two LVDS connecting pins form a transmission channel, used for transmitting data or clock. One of the LVDS connecting pins is positive output, and the other is negative output. For example, in FIG. 1, LV1P0 and LV1N0 form a data channel. These LVDS signals on the PCB will be sent to source-chip on film (S-COF) and gate-chip on film (G-COF) through a application specific integrated circuit (ASIC), and control the LCD panel (display region 12) to display the data or the images through the S-COF and G-COF. In order to avoid damaging the ASIC resulted from the static electricity appeared when the connector 11 plugs in and out, the electronic static discharge (ESD) protection chip, which is referred to as ESD protection chip hereinafter, is provided at the connection between the connector 11 and the ASIC to the important signal.
FIG. 2 shows a schematic view illustrating the structure of the connection between the ESD protection chip 22 and the ASIC. The ESD protection chip 22 is provided with several LVDS connecting pins (two groups shown in FIG. 2), a ground pin (GND) and a power pin (VDD). Each group of LVDS connecting pins is connected with one group of LVDS connecting pins on the ASIC and one group of connecting pins on the connector 21. In FIG. 2, the pin 3 of the ESD protection chip 22 is connected with the ASIC and the pin LV1P0 on the connector 21, the pin 1 is connected with the ASIC and the pin LV1P1 on the connector 21; similarly, the other group of LVDS connecting pins (pin 4 and 6) are connected with the ASIC and the pin LV1P1 and pin LVIN1 on the connector 21.
Multiple diodes connected in a certain order (D1˜D8) and zener diode D0 are provided inside the ESD protection chip 22.
It can be understood that only two groups of LVDS connecting pins are pointed out above. In the other embodiment, ESD protection chip 22 can protect more groups of LVDS connecting pins, the internal circuit of which is the same as the connection between the ASIC and the connector 21 shown in FIG. 2, which is not described in detail here.
FIG. 3 shows a schematic view illustrating the working principle of the ESD protection chip 22 shown in FIG. 2.
Take LV1P0 signal transmitted to the ASIC as example. Assume the characteristics of the diodes inside the ESD protection chip 22 are the same, the forward conduction voltage drop is UD+ (such as 0.7V), and the reverse blocking voltage drop is UD− (such as 3V). Wherein, in the LVDS transmitting circuit, assume the voltage value of the transmission signal is U (such as 1.2V), the relationship between these three is UD+<U<UD−. When the normal LVDS signal is put into the connected LV1P0 connecting pins under normal condition, the zener diode D0 inside the ESD chip is under reverse blocking state. Therefore, the signal transmission route is shown as thick black line in FIG. 3, the signal can be normally transmitted to the ASIC pin LV1P0.
FIG. 4 shows a schematic view illustrating the working principle of the abnormal soldering of the ESD protection chip 22 shown in FIG. 2.
Take LV1P0 signal transmitted to the ASIC as example. When the ESD protection chip 22 is reversely soldered on the PCB plate, the signal transmission route is shown as thick black line in FIG. 4. When the normal LVDS signal is put into the LV1P0 connecting pins of the connector 21, the transmitted signal flows into the ground via the diode D1. At the moment, the voltage distortion at the ASIC pin LV1P0 is the conduction voltage drop UD+ of the diode D1, which causes the abnormal signal output to the liquid crystal panel and results the abnormal display.
The existing detection of abnormally soldering of the ESD protection chip can only be achieved by visual observation. But the positive and negative signs of the ESD protection chip 22 are difficult to identify. Therefore, the abnormal products (the products soldered abnormally) is hard to be separated from the normal product (the products soldered correctly) by only using visual observation, which will result in the assembly problems.